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Semiconductor
Semiconductor MSM6789A/6789L
GENERAL DESCRIPTION
MSM6789A/6789L
SBC Solid-State Recorder IC
The MSM6789A/6789L, an improved version of MSM6788, is a solid-state recorder developed using the Sub Band Coding (SBC) method. Just like MSM6788, the MSM6789A/6789L has a stand-alone mode and a microcontroller interface mode. In the stand-alone mode, record/playback conditions can be selected from pins and the MSM6789A/6789L can be controlled by a simple drive timing. In the microcontroller interface mode, record/playback can be controlled by commands from the microcontroller, and more functions are available than in the stand-alone mode. The MSM6789A/6789L can directly drive serial voice ROM as external memory as well as serial register or general-purpose DRAM* (1-bit or 4-bit type selectable) as external memories, which allows a recording and playback circuit with fixed messages to be built easily. The method from microcontroller is the same as the MSM6788. * Only for MSM6789A * Difference between MSM6788 and MSM6789A MSM6788 MSM6789A General DRAM Unavailable Available Unvoiced-part elimination function No Yes PCM playback No Yes * SBC method: The SBC method divides voice frequencies into five bands and codes the component for each of the bands separately, as shown below.
@fs=8.0 Hz Gain ch 1 ch 2 ch 3
ch 4
ch 5 3 kHz
0
1
2 f (Hz)
Note:
This data sheet explains a stand-alone mode and a microcontroller interface mode, separately.
MSM6789A/6789L
Semiconductor
* Difference between MSM6789A and MSM6789L
Parameter Operating voltage External memory 4.5 to 5.5 V General-purpose DRAM, 32 Mbits (max.) 1-Mbit DRAM (MSM514256B, MSM511000B) 4-Mbit DRAM (MSM514400C, MSM514100C) 16-Mbit DRAM (MSM511740CA, MSM5116100A) ARAM*, 32 Mbits (max.) Serial register, 32 Mbits (max.) 4 Mbits (MSM6684B) 8 Mbits (MSM6685) MSM6789A MSM6789L 3.0 to 3.6 V 16 Mbits (max.) 4 Mbits (MSM66V84B)
*
Use ARAM which has no failed bits in its first 64 Kbits.
Semiconductor
MSM6789A/6789L
STAND-ALONE MODE
FEATURES
* SBC method * Built-in 12-bit AD converter * Built-in 12-bit DA converter * Built-in microphone amplifier * Built-in low-pass filter Attenuation characteristics -40 dB/oct * External memories MSM6789A (5 V version) General-purpose DRAM, 32 Mbits maximum (for variable messages) 1-Mbit DRAM : Can be directly driven (MSM514256B, MSM511000B) 4-Mbit DRAM : Can be directly driven (MSM514400C, MSM514100C) 16-Mbit DRAM : Can be directly driven (MSM5117400A, MSM5116100A) ARAM, 32 Mbits maximum (for variable messages) Note :Use the first 64 Kbits with no failed bits for the ARAM. Serial register, 32 Mbits maximum (for variable messages) 4-Mbit serial register : Can be directly driven (MSM6684B) 8-Mbit serial register : Can be directly driven (MSM6685) MSM6789L (3.3 V version) Serial register, 16 Mbits maximum (for variable messages) 4-Mbit serial resister: Can be directly driven (MSM66V84B) MSM6789A (5 V version) and MSM6789L (3.3 V version) Serial voice ROM, 4 Mbits maximum (for fixed messages) 1-Mbit serial voice ROM : Can be directly driven (MSM6595A) 2-Mbit serial voice ROM : Can be directly driven (MSM6596A) 3-Mbit serial voice ROM : Can be directly driven (MSM6597A) * Bit rate 10.0, 12.6, 16.0 kbps (at 8 kHz sampling freq.) 7.5, 9.5, 12.0 kbps (at 6 kHz sampling freq.) * Maximum recording time (when one 8-Mbit serial register is connected) 13.8 minutes (for 10.0 kbps SBC) 18.4 minutes (for 7.5 kbps SBC) 11.0 minutes (for 12.6 kbps SBC) 14.6 minutes (for 9.5 kbps SBC) 8.6 minutes (for 16.0 kbps SBC) 11.5 minutes (for 12.0 kbps SBC) * Number of phrases 63 phrases for variable messages 63 phrases for fixed messages * Standard linear PCM playback or OKI nonlinear PCM playback can be selected. * Voice triggered starting function (voice detect level can be set) * Unvoiced-part elimination function (voice detect level can be set) * Pausing function * Master clock frequency: 6.0 MHz to 8.192 MHz * Power supply voltage: MSM6789A : Single 5 V power supply MSM6789L : Single 3.3 V power supply * Package options: MSM6789A : 100-pin plastic QFP (QFP100-P-1420-BK) (Product name: MSM6789AGS-BK) MSM6789L : 100-pin plastic QFP (QFP100-P-1420-BK) (Product name: MSM6789LGS-BK)
DEL ST SP CA0CA1CA2CA3CA4CA5
PAUSE VDS VD0 VD1VD2VD3
TMD0 to TMD3 TMD4 TST TCK TEST TEST SYNC
MSM6789A/6789L
MCUM
Compare Circuit Phrase Register Test Circuit
RESET Data I/O Address Controller
PDWN
PDMD
Timing
DRAM/SR
Controller
TDT4 to TDT7 TDT0 to TDT3 [DQ1 to DQ4] DI/O DROM
4B/1B
ROM
MON
NAR
BLOCK DIAGRAM (for MSM6789A (5 V Version))
XT XT SBC Analyzer/Synthesizer
Memory Controller
OSC
REC/PLAY BR0 BR1 PCM Synthesizer
Latch
MIN
-
MSEL1 MSEL2 RSEL1 RSEL2 A0(SADY) A1(SADX) A2(TAS) A3(SAS) A4(RWCK) A5 to A10 RAS CAS0 to CAS7 WE CS1 CS2 CS3 CS4
+ LPF OSC (RC) 12-bit DAC SG Circuit LOWPWR DVDD AVDD DGND AGND AOUT FOUT ADIN SG SGC
MOUT 12-bit ADC
LIN
- +
Semiconductor
LOUT
AMON FIN
Semiconductor
MSM6789A/6789L
PIN CONFIGURATION (TOP VIEW) (for MSM6789A (5 V Version))
CAS7 CAS6 CAS5 CAS4 CAS3 CAS2 CAS1 CAS0 XT XT DVDD RAS 4B/1B LOWPWR NC DROM CS4 CS3 CS2 CS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A10 A9 A8 A7 A6 A5 NC TMD4 TMD3 TMD2 TMD1 TMD0 TDT7 TDT6 TDT5 TDT4 TDT3 TDT2 TDT1 TDT0 SYNC TST TCK CA0 CA1 CA2 CA3 NC CA4 CA5
[DQ4] [DQ3] [DQ2] [DQ1]
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC A0 (SADY) A1 (SADX) A2 (TAS) A3 (SAS) A4 (RWCK) WE DI/O MON NAR VD3 VD2 VD1 VD0 DRAM/SR REC/PLAY ST SP RESET TEST PDWN MSEL2 MSEL1 RSEL2 RSEL1 DGND AGND MIN MOUT LIN
DEL PAUSE PDMD MCUM BR0 BR1 TEST VDS ROM DGND NC ADIN FOUT
100-Pin Plastic QFP ( ): [ ]: NC : Pins for connecting serial voice ROM Pins for connecting 4-bit type DRAM No-connection pin
AOUT FIN AMON AVDD SG SGC LOUT
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MSM6789A/6789L
Semiconductor
PIN DESCRIPTIONS (for MSM6789A (5 V Version))
Pin 90 47 40, 55 54 48, 49 53 51 52 50 46 45 43 42 44 Symbol Type DVDD AVDD DGND AGND SG, SGC MIN LIN MOUT LOUT AMON FIN FOUT ADIN AOUT -- -- -- -- -- I O O I O I O pin and the DGND pin. Analog power supply. Insert a bypass capacitor of 0.1 mF or more between this pin and the AGND pin. Digital ground. Analog ground. Output for analog circuit reference voltage (signal ground). Inverting input of the built-in OP amplifier. The non-inverting input pin is internally connected to SG (signal ground). Output of the built-in OP amplifier for MIN and LIN. Connected to the LOUT pin in the recording mode and to the DA converter output in the playback mode. This pin connects the built-in LPF input (FIN pin). Input of the built-in LPF. Output of the built-in LPF. This pin connects the AD converter input (ADIN pin). Input of the built-in 12-bit AD converter. Output of the built-in LPF. This pin outputs playback waveforms and connects an external speaker drive amplifier. This pin selects whether memory to be connected externally is DRAM or serial register. 66 DRAM/SR I Low level : Serial register High level : DRAM This pin selects either 1-bit type DRAM or 4-bit type DRAM. 88 4B/1B I Low level : 1-bit type High level : 4-bit type 79 78 A0 (SADY) A1 (SADX) These pins connect to A0 and A1 of DRAM at the time of DRAM selection. They also O connect to SAD pin of serial register and serial voice ROM at the time of serial register selection. These pins output leading addresses of read/write. This pin connects to A2 of DRAM at the time of DRAM selection. It also connects 77 A2 (TAS) O to TAS pin of serial register and serial voice ROM at the time of serial register selection. This pin is used to set serial addresses from the SADX and SADY pins into the internal address counter of the serial register and serial voice ROM. This pin connects to A3 of DRAM at the time of DRAM selection. It also connects 76 A3 (SAS) O to the SAS pin of the serial register and the SASX and SASY pins of the serial voice ROM at the time of serial register selection. Clock pin to write serial addresses. This pin connects to A4 of DRAM at the time of DRAM selection. It also connects 75 A4 (RWCK) O to the RWCK pin of the serial register and the RDCK pin of the serial voice ROM at the time of serial register selection. Clock pin to read data from and write data into the serial register. 1-6 A10-A5 O This pin connects to pins A5-A10 of DRAM at the time of DRAM selection. This pin outputs addresses of read/write. Description Digital power supply. Insert a bypass capacitor of 0.1 mF or more between this
Semiconductor
MSM6789A/6789L
PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued)
Pin 74 73 85 89 93-100 81 82 83 84 58 59 Symbol WE DI/O DROM RAS CAS0CAS7 CS1 CS2 CS3 CS4 MSEL1 MSEL2 I I These pins select the capacity of the memory to be connected externally. These pins select the number of DRAMs and serial registers to be connected externallly. * When DRAM is selected (DRAM/SR = High level) MSEL2 L L L L L L 56 57 RSEL1 RSEL2 I I L L H H H H H H H H MSEL1 L L L L H H H H L L L L H H H H RSEL2 L L H H L L H H L L H H L L H H RSEL1 L H L H L H L H L H L H L H L H Memory capacity 1M 4 4M 1 1M 8 1M 4 + 4M 1 4M 2 4M 2 4M 3 4M 3 4M 4 16M 1 4M 6 4M 6 4M 8 4M 8 16M 2 16M 2 O Chip Select. These pins connect to CS pin of the serial register and the CS (CS1, CS2, CS3) pins of the serial voice ROM. Type O I/O I O O Description Write Enable. This pin connects to the WE pin of the serial register and DRAM. This pin selects either read or write mode. Data I/O. This pin connects to the DIN and DOUT pins of the serial register and DRAM. This pin outputs write data and inputs read data. Data ROM. This pin connects to the DOUT pin of the serial voice ROM. This is a row address strobe pin of DRAM at the time of DRAM selection. These are the column address strobe pins of DRAM at the time of DRAM selection. CAS7, an addresss output pin, is connected to pin A11 of DRAM at the time 16-Mbit DRAM selection.
MSM6789A/6789L
Semiconductor
PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued)
Pin Symbol Type Description * When serial register is selected (DRAM/SR = Low level) MSEL2 L L 56 57 RSEL1 RSEL2 I I L L L L L L MSEL1 L L L L H H H H RSEL2 L L H H L L H H RSEL1 L H L H L H L H Memory capacity 4M 1 4M 2 4M 3 4M 4 8M 1 8M 2 8M 3 8M 4
This pin selects CAS-before-RAS refresh period of DRAM at the time of 87 LOWPWR I power down when DRAM is selected. Low level : 15 s max. High level : 125 s max. Mode Selection. 34 MCUM I Low level : Stand-alone mode High level : Microcontroller interface mode 62 RESET I A high input level causes the MSM6789A to be initialized and to go into the power down state. Power Down. When a low level is input, the MSM6789A goes to the power down state. Unlike the RESET pin, this pin does not force the MSM6789A to be reset. 60 PDWN I When a Low level is applied to this pin during recording operation, the MSM6789A is halted, and will be maintained in the power down state while PDWN is low level. After this pin is restored to a high level, postprocessing for recording will be performed. 91 92 37 61 9-12 13-20 21 17-20 22 23 8 XT XT TEST TEST
TMD3-TMD0 TDT7-TDT0 SYNC TDT3-TDT0 [DQ4]-[DQ1]
I O I
Oscillator Connection. When an external clock is used, input the clock through this pin. During the power down state, this pin must be set to the ground level. Oscillator Connection. When an external clock is used, this pin must be left open. MSM6789A Test. Input a low level to the TEST pin and a high level to the TEST pin.
I/O
MSM6789A Test. This pin must be left open. Connect these pins to DQ1-DQ4 of DRAM at the time of 4-bit type DRAM selection. Otherwise these pins must be left open as they are MSM6789A test pins. MSM6789A Test. Input a low level signal.
I/O
TST TCK TMD4 I
Semiconductor
MSM6789A/6789L
PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued)
Pin 39 Symbol ROM Type I Description Playback Operation. When set to low, this pin selects the record/playback operation (only for the SBC method). When set to high, it selects the ROM playback operation (for the SBC and PCM methods). Recording mode or playback mode selection. This pin is invalid during 65 REC/PLAY I the ROM playback operation. When set to low, it selects the playback mode. When set to high, it selects the recording mode. 64 63 32 ST SP PAUSE I I I Start Playback. When a low-level pulse is applied to this pin, the record/playback or ROM playback is started. Stop Playback.When a low-level pulse is applied to this pin, the record/playback or ROM playback is stopped. Playback Pause. When a low-level pulse is applied to this pin, the record/playback or ROM operation is stopped temporarily. Phrase Delection. When a low level pulse is applied to this pin, all phrase deletion or specified phrase deletion can be performed according to the setting of pins CA0 31 DEL I through CA5, ch00:All phrase deletion ch01 to ch3F:Specified phrase deletion After power up, be sure to input a RESET signal and then delete all phrases. After completing this procedure, start the record/playback operation. Desired Phrase Specification. A total of 63 phrases can be specified indepedently for the record/playback operation and the ROM playback operation. CA5 CA4 CA3 CA2 CA1 CA0 L 24-30 CA0-CA5 I L L . . . H H L L L . . . H H L L L . . . H H L L L . . . H H L L H . . . H H L H L . . . L H Phrase No. ch00 ch01 ch02 . . . ch3E ch3F A total of 63 phrases can be used for both record /playback and ROM playback operation. Remarks All phrase deletion
MSM6789A/6789L
Semiconductor
PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued)
Pin Symbol Type Description Bit Rate Selection. This pin selects one of the following three types of bit rate (master clock frequency fOSC = 8.192 MHz). This pin is invalid during the ROM playback operation. BR1 35 36 BRO BR1 I L L H H BR0 L H L H Bit rate 16.0 kbps 12.6 kbps 10.0 kbps Unused
Transition to the Power-down State. Low level: The MSM6789A automatically goes to the power-down state, except when the record/playback operation is performed. High level: The MSM6789A automatically goes to the standby state, instead of the 33 PDMD*1 I power-down state, except when the record/playback operation is performed. In this case, the MSM6789A can be placed in the power-down state by setting the RESET or PDWN pin to a high level. If an external circuit is used for the built-in LPF, this standby mode must be selected by applying a high level to the PDMD pin. 67-70 VD0-VD3 I These pins set the voice detect level for the voice triggered starting and unvoiced-part elimination. This pin selects the voice triggered starting or the unvoiced-part elimination. Voice triggered starting: 38 VDS I Input a High level to the VDS pin. Then set the voice detect level with VD0 to VD3 pins. Unvoiced-part elimination:Input a Low level to the VDS pin. Then set the voice detect level with VD0 to VD3 pins. Note: When neither the voice triggered starting nor the unvoiced-part elimination is used, input a Low level to VD0 to VD3. 72 71 MON NAR O O This pin outputs a high level while the record/playback operation is being performed. Output to indicate the enable or disable state of the operation for specifying a phrase. When continuous ROM playback is performed, the next phrase can be specified after the NAR pin goes to high positively.
*1 When DRAM is selected, be sure to set the PDMD pin to a High level.
Semiconductor
MSM6789A/6789L
ABSOLUTE MAXIMUM RATINGS (for MSM6789A (5 V Version))
Parameter Power supply voltage Input voltage Storage temperature Symbol V DD V IN T STG Condition Ta=25C Ta=25C -- Rating -0.3 to +7.0 -0.3 to VDD +0.3 -55 to +150 Unit V V C
RECOMMENDED OPERATING CONDITIONS (for MSM6789A (5 V Version))
Parameter Power supply voltage Operating temperature Master clock frequencuy Symbol VDD Top fOSC Condition DGND=AGND=0 V -- -- Range +3.5 to +5.5*4 0 to +70 6.0 to 8.192 Unit V C MHz
ELECTRICAL CHARACTERISTICS (for MSM6789A (5 V Version))
DC Characteristics
Parameter High input voltage Low input voltage High output voltage Low output voltage High input current *1 High input current
*2
DVDD=AVDD=4.5 to 5.5 V*4 DGND=AGND=0 V, Ta=0 to 70C Symbol V IH V IL V OH V OL IIH1 IIH2 IIL1 IIL2 IIL3 I DD IDDS1 IOH=-40 mA IOL=2 mA VIH=VDD VIH=VDD VIL=GND VIL=GND VIL=GND fOSC=8 MHz, no load No load Serial register connected No load DRAM connected Condition -- -- Min. 0.8VDD -- V DD-0.3 -- -- -- -10 -20 -400 -- -- -- Typ. -- -- -- -- -- -- -- -- -- 20 -- 200 Max. -- 0.2VDD -- 0.45 10 20 -- -- -20 35 10 -- V V mA mA mA mA mA mA mA mA Unit V V
Low input currcent *1 Low input current *2 Low input current *3 Operating current consumption
Power down current IDDS2
*1 *2 *3 *4
Applies to all inputs excluding the XT pin. Applies to the XT pin. Applies to the input pins with pull-up resistor (ST, SP, PAUSE, DEL) excluding the XT pin. The record/playback operation must be performed at the power supply voltage of 4.5 to 5.5 V. The MSM6789A operates at 3.5 to 5.5 V when the serial register is backed up.
MSM6789A/6789L
Semiconductor
Analog Characteristics
Parameter DA output relative error FIN admissible input voltage range FIN input impedance Op-map open loop gain Op-amp input impedance Op-amp load resistance AOUT load resistance FOUT load resistance Symbol VDAE V FIN R FIN G OP R INA R OUTA R AOUT R FOUT Condition no load -- -- fIN=0 to 4kHz -- -- -- --
DVDD=AVDD=4.5 to 5.5 V DGND=AGND=0 V Ta=0 to 70C Min. -- 1 1 40 1 200 50 50 Typ. -- -- -- -- -- -- -- -- Max. 10 VDD-1 -- -- -- -- -- -- Unit mV V MW dB MW kW kW kW
TMD0 to DEL ST SP PAUSE VDS VD0 VD1 VD2 VD3 CA0 CA1 CA2 CA3 CA4 CA5 TMD3 TMD4 TST TCK TEST TEST SYNC
Compare Circuit Phrase Register Test Circuit
MCUM
Semiconductor
RESET Data I/O Address Controller
PDWN
Timing
PDMD
Controller
TDT4 to TDT7 TDT0 to TDT3 DI/O DROM MSEL1 MSEL2 RSEL1 RSEL2 SADY SADX TAS
ROM
MON
NAR
XT XT SBC Analyzer/Synthesizer
BLOCK DIAGRAM (for MSM6789L (3.3 V Version))
Memory Controller
OSC
SAS RWCK WE CS1 CS2 CS3
REC/PLAY BR0 BR1
Latch PCM Synthesizer
MIN
-
CS4
+ LPF
MOUT 12-bit ADC 12-bit DAC SG Circuit DVDD AVDD DGND AGND AOUT FOUT ADIN SG SGC
LIN
- +
MSM6789A/6789L
LOUT
AMON FIN
MSM6789A/6789L
Semiconductor
PIN CONFIGURATION (TOP VIEW) (for MSM6789L (3.3 V Version))
TEST TEST NC DROM CS4 CS3 CS2 CS1 NC NC NC NC NC NC NC NC XT XT DVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC NC NC NC NC NC NC TMD4 TMD3 TMD2 TMD1 TMD0 TDT7 TDT6 TDT5 TDT4 TDT3 TDT2 TDT1 TDT0 SYNC TST TCK CA0 CA1 CA2 CA3 NC CA4 CA5
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC SADY SADX TAS SAS RWCK WE DI/O MON NAR VD3 VD2 VD1 VD0 TEST REC/PLAY ST SP RESET TEST PDWN MSEL2 MSEL1 RSEL2 RSEL1 DGND AGND MIN MOUT LIN
DEL PAUSE PDMD MCUM BR0 BR1 TEST VDS ROM DGND NC ADIN FOUT
100-Pin Plastic QFP NC : No-connection pin
AOUT FIN AMON AVDD SG SGC LOUT
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Semiconductor
MSM6789A/6789L
PIN DESCRIPTIONS (for MSM6789L (3.3 V Version))
Pin 90 47 40, 55 54 48, 49 53 51 52 50 46 45 43 42 44 79 78 77 Symbol Type DVDD AVDD DGND AGND SG, SGC MIN LIN MOUT LOUT AMON FIN FOUT ADIN AOUT SADY SADX TAS -- -- -- -- -- I O O I O I O O pin and the DGND pin. Analog power supply. Insert a bypass capacitor of 0.1 mF or more between this pin and the AGND pin. Digital ground. Analog ground. Output for analog circuit reference voltage (signal ground). Inverting input of the built-in OP amplifier. The non-inverting input pin is internally connected to SG (signal ground). Output of the built-in OP amplifier for MIN and LIN. Connected to the LOUT pin in the recording mode and to the DA converter output in the playback mode. This pin connects the built-in LPF input (FIN pin). Input of the built-in LPF. Output of the built-in LPF. This pin connects the AD converter input (ADIN pin). Input of the built-in 12-bit AD converter. Output of the built-in LPF. This pin outputs playback waveforms and connects an external speaker drive amplifier. They also connect to SAD pin of serial register and serial voice ROM. These pins output leading addresses of read/write. This pin connects to TAS pin of serial register and serial voice ROM. O This pin is used to set serial addresses from the SADX and SADY pins into the internal address counter of the serial register and serial voice ROM. 76 75 74 73 85 81 82 83 84 SAS RWCK WE DI/O DROM CS1 CS2 CS3 CS4 O Chip Select. These pins connect to CS pin of the serial register and the CS (CS1, CS2, CS3) pins of the serial voice ROM. O O O I/O I This pin connects to the SAS pin of the serial register and the SASX and SASY pins of the serial voice ROM. Clock pin to write serial addresses. This pin connects to the RWCK pin of the serial register and the RDCK pin of the serial voice ROM. Clock pin to read data from and write data into the serial register. Write Enable. This pin connects to the WE pin of the serial register and DRAM. This pin selects either read or write mode. Data I/O. This pin connects to the DIN and DOUT pins of the serial register and DRAM. This pin outputs write data and inputs read data. Data ROM. This pin connects to the DOUT pin of the serial voice ROM. Description Digital power supply. Insert a bypass capacitor of 0.1 mF or more between this
MSM6789A/6789L
Semiconductor
PIN DESCRIPTIONS (for MSM6789L (3.3 V Version)) (Continued)
Pin 58 59 Symbol MSEL1 MSEL2 Type I I Description These pins select the capacity of the memory to be connected externally. These pins select the number of and serial registers to be connected externallly. MSEL2 56 57 RSEL1 RSEL2 I I L L L L Mode Selection. 34 MCUM I Low level : Stand-alone mode High level : Microcontroller interface mode 62 RESET I A high input level causes the MSM6789L to be initialized and to go into the power down state. Power Down. When a low level is input, the MSM6789L goes to the power down state. Unlike the RESET pin, this pin does not force the MSM6789L to be reset. 60 PDWN I When a Low level is applied to this pin during recording operation, the MSM6789L is halted, and will be maintained in the power down state while PDWN is low level. After this pin is restored to a high level, postprocessing for recording will be performed. 91 92 37 61 9-12 13-20 21 17-20 22 23 8 XT XT TEST TEST
TMD3-TMD0 TDT7-TDT0 SYNC TDT3-TDT0
MSEL1 L L L L
RSEL2 L L H H
RSEL1 L H L H
Memory capacity 4M 1 4M 2 4M 3 4M 4
I O I
Oscillator Connection. When an external clock is used, input the clock through this pin. During the power down state, this pin must be set to the ground level. Oscillator Connection. When an external clock is used, this pin must be left open. MSM6789L Test. Input a low level to the TEST pin and a high level to the TEST pin.
I/O I/O I
MSM6789L Test. This pin must be left open. These pins must be left open as they are MSM6789L test pins. MSM6789L Test. Input a low level signal.
TST TCK TMD4
Semiconductor
MSM6789A/6789L
PIN DESCRIPTIONS (for MSM6789L (3.3 V Version)) (Continued)
Pin 39 Symbol ROM Type I Description Playback Operation. When set to low, this pin selects the record/playback operation (only for the SBC method). When set to high, it selects the ROM playback operation (for the SBC and PCM methods). Recording mode or playback mode selection. This pin is invalid during 65 REC/PLAY I the ROM playback operation. When set to low, it selects the playback mode. When set to high, it selects the recording mode. 64 63 32 ST SP PAUSE I I I Start Playback. When a low-level pulse is applied to this pin, the record/playback or ROM playback is started. Stop Playback.When a low-level pulse is applied to this pin, the record/playback or ROM playback is stopped. Playback Pause. When a low-level pulse is applied to this pin, the record/playback or ROM operation is stopped temporarily. Phrase Delection. When a low level pulse is applied to this pin, all phrase deletion or specified phrase deletion can be performed according to the setting of pins CA0 31 DEL I through CA5, ch00:All phrase deletion ch01 to ch3F:Specified phrase deletion After power up, be sure to input a RESET signal and then delete all phrases. After completing this procedure, start the record/playback operation. Desired Phrase Specification. A total of 63 phrases can be specified indepedently for the record/playback operation and the ROM playback operation. CA5 CA4 CA3 CA2 CA1 CA0 L 24-30 CA0-CA5 I L L . . . H H L L L . . . H H L L L . . . H H L L L . . . H H L L H . . . H H L H L . . . L H Phrase No. ch00 ch01 ch02 . . . ch3E ch3F A total of 63 phrases can be used for both record /playback and ROM playback operation. Remarks All phrase deletion
MSM6789A/6789L
Semiconductor
PIN DESCRIPTIONS (for MSM6789L (3.3 V Version)) (Continued)
Pin Symbol Type Description Bit Rate Selection. This pin selects one of the following three types of bit rate (master clock frequency fOSC = 8.192 MHz). This pin is invalid during the ROM playback operation. BR1 35 36 BRO BR1 I L L H H BR0 L H L H Bit rate 16.0 kbps 12.6 kbps 10.0 kbps Unused
Transition to the Power-down State. Low level: The MSM6789L automatically goes to the power-down state, except when the record/playback operation is performed. High level: The MSM6789L automatically goes to the standby state, instead of the 33 PDMD*1 I power-down state, except when the record/playback operation is performed. In this case, the MSM6789L can be placed in the power-down state by setting the RESET or PDWN pin to a high level. If an external circuit is used for the built-in LPF, this standby mode must be selected by applying a high level to the PDMD pin. 67-70 VD0-VD3 I These pins set the voice detect level for the voice triggered starting and unvoiced-part elimination. This pin selects the voice triggered starting or the unvoiced-part elimination. Voice triggered starting: 38 VDS I Input a High level to the VDS pin. Then set the voice detect level with VD0 to VD3 pins. Unvoiced-part elimination:Input a Low level to the VDS pin. Then set the voice detect level with VD0 to VD3 pins. Note: When neither the voice triggered starting nor the unvoiced-part elimination is used, input a Low level to VD0 to VD3. 72 71 MON NAR O O This pin outputs a high level while the record/playback operation is being performed. Output to indicate the enable or disable state of the operation for specifying a phrase. When continuous ROM playback is performed, the next phrase can be specified after the NAR pin goes to high positively.
*1 When DRAM is selected, be sure to set the PDMD pin to a High level.
Semiconductor
MSM6789A/6789L
ABSOLUTE MAXIMUM RATINGS (for MSM6789L (3.3 V Version))
Parameter Power supply voltage Input voltage Storage temperature Symbol VDD VIN TSTG Condition Ta=25C Ta=25C -- Rating -0.3 to +7.0 -0.3 to VDD +0.3 -55 to +150 Unit V V C
RECOMMENDED OPERATING CONDITIONS (for MSM6789L (3.3 V Version))
Parameter Power supply voltage Operating temperature Master clock frequencuy Symbol VDD Top fOSC Condition DGND=AGND=0 V -- -- Range +3.0 to +3.6 0 to +70 6.0 to 8.192 Unit V C MHz
ELECTRICAL CHARACTERISTICS (for MSM6789L (3.3 V Version))
DC Characteristics
Parameter High input voltage Low input voltage High output voltage Low output voltage High input current *1 High input current
*2
DVDD=AVDD=3.0 to 3.6 V DGND=AGND=0 V, Ta=0 to 70C Symbol V IH V IL V OH V OL IIH1 IIH2 IIL1 IIL2 IIL3 I DD IDDS1 IOH=-40 mA IOL=2 mA VIH=VDD VIH=VDD VIL=GND VIL=GND VIL=GND fOSC=8 MHz, no load No load Serial register connected No load DRAM connected Condition -- -- Min. 0.85VDD -- V DD-0.3 -- -- -- -10 -20 -400 -- -- -- Typ. -- -- -- -- -- -- -- -- -- 20 -- 200 Max. -- 0.15VDD -- 0.45 10 20 -- -- -20 35 10 -- V V mA mA mA mA mA mA mA mA Unit V V
Low input currcent *1 Low input current *2 Low input current
*3
Operating current consumption
Power down current IDDS2
*1 Applies to all inputs excluding the XT pin. *2 Applies to the XT pin. *3 Applies to the input pins with pull-up resistor (ST, SP, PAUSE, DEL) excluding the XT pin.
MSM6789A/6789L
Semiconductor
Analog Characteristics
Parameter DA output relative error FIN admissible input voltage range FIN input impedance Op-map open loop gain Op-amp input impedance Op-amp load resistance AOUT load resistance FOUT load resistance Symbol VDAE VFIN RFIN GOP RINA ROUTA RAOUT RFOUT Condition no load -- -- fIN=0 to 4kHz -- -- -- --
DVDD=AVDD=3.0 to 3.6 V DGND=AGND=0 V Ta=0 to 70C Min. -- 1 1 40 1 400 100 100 Typ. -- -- -- -- -- -- -- -- Max. 20 VDD-1 -- -- -- -- -- -- Unit mV V MW dB MW kW kW kW
DVDD REC/PLAY VCC
SADX
AVDD VCC SADX SASX SADY
DEL MSM6685 SADX SAS SADY TAS RWCK SASY TAS RDCK MSM6685 MSM6685 SAS SAS SAD
SADX
SAS
ST SP PAUSE 8M Serial Register TAS RWCK WE DI/O DROM DOUT TEST
CS1 CS2 VSS
MSM6596A-XXX
SADY 2M Serial Voice ROM MSM6596A-XXX TAS
Semiconductor
RESET TAS PDWN RWCK TEST MSEL1 WE MSEL2 DI/O DRAM/SR RSEL1 RSEL2 BR0 DROM BR1 A5-A10 PDMD MCUM RAS LOWPWR TEST CAS0-CAS7 4B/1B RWCK WE DIN DOUT TEST RFSH NC RS/A CS VSS MSM6685
VDS
CS1
DVDD
CS2
CS3
RECORDER IC
HEX SW
VD3 VD2 VD1 VD0
CS4
MIN
APPLICATION CIRCUITS (for MSM6789A (5 V version))
MSM6789A
SW Phrase Selection
MOUT
CA5 CA4 CA3 CA2 CA1 CA0 TST TCK TMD4
LIN
ROM
XT
Speaker drive amplifier
8.192 MHz
XT
LOUT AMON FIN FOUT ADIN AOUT
SGC
MON NAR SYNC TDT0-7 TMD0-3
SG
+
+
MSM6789A/6789L
This is an application circuit example when the MSM6789A is used in stand-alone mode with four 8-Mbit serial registers and two 2-Mbit serial voice ROMs.
DGND
AGND
Circuit 1 :
Application circuit in stand-alone mode with 8-Mbit serial registers and 2-Mbit serial voice ROMs.
DVDD REC/PLAY VCC SADX SADX SASX SADY SAS SADY TAS RWCK
AVDD
VCC
VCC
VCC
VCC
DEL
MSM514100C
MSM514100C
MSM6596A-XXX
MSM514100C
ST SASY TAS RDCK 2M Serial Voice ROM MSM6596A-XXX
MSM6789A/6789L
SP
PAUSE
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 WE DI/O 4-Mbit DRAM MSM514100C DROM DOUT TEST
CAS VSS CAS VSS CS1 CS2 VSS CAS VSS
A0(SADY) A1(SADX) A2(TAS) A3(SAS) A4(RWCK) A5 A6 A7 A8 A9 A10 WE DI/O DROM RAS
CAS VSS
RESET PDWN DRAM/SR TEST MSEL2 MSEL1 RSEL2 RSEL1 BR0 BR1 PDMD MCUM LOWPWR TEST 4B/1B VDS
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 WE DIN DOUT RAS
VD3
CAS0 CAS1 CAS2 CAS3 CAS4 CAS5 CAS6 CAS7
RECORDER IC
VD2
VD1
HEX SW
VD0
CS1 CS2 CS3 CS4
MSM6789A
MIN
SW Phrase Selection
CA5 CA4 CA3 CA2 CA1 CA0 LIN
MOUT
TST TCK TMD4
ROM Speaker drive amplifier
APPLICATION CIRCUITS (for MSM6789A (5 V version)) (Continued)
XT
8.192 MHz
XT
LOUT AMON FIN FOUT ADIN AOUT
SGC SG
MON NAR SYNC TDT0-7 TMD0-3
+
+
This is an application circuit example when the MSM6789A is used in stand-alone mode with four 4-Mbit DRAMs (1-bit type) and two 2-Mbit serial voice ROMs.
Semiconductor
DGND
AGND
Circuit 2 :
Application circuit in stand-alone mode with 4-Mbit DRAMs and 2-Mbit serial voice ROMs.
5 A0-A4
DVDD REC/PLAY A1(SADX) SADX SASX SADY A3(SAS) A0(SADY) A2(TAS) A4(RWCK)
AVDD
VCC VCC VCC VCC VCC VCC
DEL 11 10 A0~A A0~A9 10 10 10 2M Serial Voice ROM MSM6596A-XXX A0-A10
MSM6596A-XXX
MSM511000B
MSM511000B
MSM511000B
ST SASY TAS RDCK
SP
A0-A10
Semiconductor
PAUSE
4-Mbit DRAM MSM514100C 1-Mbit DRAM MSM511000B DROM DOUT TEST
CAS VSS CAS VSS CAS VSS CAS VSS CS1 CS2 VSS
RESET PDWN TEST DRAM/SR MSEL2 MSEL1 RSEL2 RSEL1 BR0 BR1 PDMD MCUM LOWPWR TEST 4B/1B VDS WE DIN DOUT RAS CAS VSS
WE DI/O DROM RAS
VD3
CAS0 CAS1 CAS2 CAS3 CAS4 CAS5 CAS6 CAS7
VD2
RECORDER IC CS1 CS2 CS3 CS4 MIN
VD1
HEX SW
VD0
MSM6789A
SW Phrase Selection LIN
CA5 CA4 CA3 CA2 CA1 CA0 TST TCK TMD4
MOUT
ROM Speaker drive amplifier
APPLICATION CIRCUITS (for MSM6789A (5 V version)) (Continued)
XT
8.192 MHz SGC SG
XT
LOUT AMON FIN FOUT ADIN AOUT
MON NAR SYNC TDT0-7 TMD0-3
+
+
This is an application circuit example when the MSM6789A is used in stand-alone mode with one 4-Mbit DRAM, four 1-Mbit DRAMs (1-bit type) and two 2-Mbit serial voice ROMs.
MSM6789A/6789L
DGND
AGND
Circuit 3 :
Application circuit in stand-alone mode with 4-Mbit DRAMs, 1-Mbit DRAMs and 2-Mbit serial voice ROMs.
5 A0-A4 AVDD VCC A1(SADX) SADX SASX SADY A3(SAS) A0(SADY) A2(TAS) A4(RWCK) VCC VCC DVDD REC/PLAY DEL ST 11 A0-A10 A0-A10 A11 A0-A10 A0-A10 11 SP PAUSE SASY TAS RDCK 2M Serial Voice ROM MSM6596A-XXX MSM6596A-XXX MSM5116100A DROM DOUT TEST
CAS VSS CS1 CS2 VSS
MSM6789A/6789L
16-Mbit DRAM MSM5116100A
WE DI/O DROM RAS CAS0 CAS1 CAS2 CAS3 CAS4 CAS5 CAS6 CAS7
CAS VSS
RESET PDWN TEST DRAM/SR MSEL2 MSEL1 RSEL2 RSEL1 BR0 BR1 PDMD MCUM TEST LOWPWR 4B/1B VDS VD3 WE DIN DOUT RAS VD2 VD1 VD0 MSM6789A MIN MOUT RECORDER IC
HEX SW
CS1 CS2 CS3 CS4
SW Phrase Slection
CA5 CA4 CA3 CA2 CA1 CA0 TST TCK TMD4 LIN ROM XT XT
APPLICATION CIRCUITS (for MSM6789A (5 V version)) (Continued)
8.192 MHz
LOUT AMON FIN FOUT ADIN AOUT SGC SG
Speaker Drive Amplifier
MON NAR SYNC TDT0-7 TMD0-3
+
+
This is an application circuit example when the MSM6789A is used in stand-alone mode with two 16-Mbit DRAMs (1-bit type) and two 2-Mbit serial voice ROMs.
Semiconductor
DGND
AGND
Circuit 4 :
Application circuit in stand-alone mode with 16Mbit DRAMs, and 2-Mbit serial voice ROMs.
5
A0-A4
DVDD REC/PLAY AVDD VCC A1(SADX) SADX SASX SADY A3(SAS) A0(SADY) A2(TAS) A4(RWCK) 10 10 A0~A9 10 10
VCC
VCC
VCC
VCC
VCC
DEL
MSM514400C
MSM514400C
MSM514400C
ST
A0-A9 A10
MSM6596A-XXX
SP
PAUSE
SASY TAS RDCK 2M Serial Voice ROM MSM6596A-XXX
Semiconductor
RESET
[TDT0]DQ1 [TDT1]DQ2 [TDT2]DQ3 [TDT3]DQ4
DQ1 DQ2 DQ3 DQ4
4-Mbit DRAM MSM514400C DOUT TEST
WE RAS DI/O DROM WE RAS OE
CAS VSS CAS VSS CAS VSS CS1 CS2 VSS CAS VSS
PDWN DRAM/SR TEST 4B/1B MSEL2 MSEL1 RSEL2 RSEL1 BR0 BR1 PDMD MCUM LOWPWR TEST CAS0 CAS1 CAS2 CAS3 CAS4 CAS5 CAS6 CAS7
VDS
VD3
VD2
VD1
HEX SW MIN
RECORDER IC MSM6789A CS1 CS2 CS3 CS4
VD0
SW Phrace Slection
MOUT
CA5 CA4 CA3 CA2 CA1 CA0 TST TCK TMD4 LIN
ROM Speaker Drive Amplifier
APPLICATION CIRCUITS (for MSM6789A (5 V version)) (Continued)
XT
8.192 MHz
XT
LOUT AMON FIN FOUT ADIN AOUT SGC SG
MON NAR SYNC TDT4-7 TMD0-3
+
+
MSM6789A/6789L
This is an application circuit example when the MSM6789A is used in stand-alone mode with four 4-Mbit DRAMs (4-bit type) and two 2-Mbit serial voice ROMs.
DGND
AGND
Circuit 5 :
Application circuit in stand-alone mode with 4-Mbit DRAMs and 2-Mbit serial voice ROMs.
5 A0-A4
DVDD REC/PLAY A1(SADX) SADX SASX SADY A3(SAS) A0(SADY) A2(TAS) 10 9 A0-A8 SASY TAS A4(RWCK) RDCK 2M Serial Voice ROM MSM6596A-XXX 9 9 9 A0-A9 DQ1 DQ2 DQ3 DQ4 WE OE DOUT TEST
CAS VSS CAS VSS CAS VSS CAS VSS CS1 CS2 VSS
AVDD VCC VCC VCC VCC VCC
VCC
DEL
MSM6596A-XXX
MSM514256B
MSM514256B
MSM514256B
ST
A0-A9
SP
A10
MSM6789A/6789L
PAUSE
[TDT0]DQ1 [TDT1]DQ2 [TDT2]DQ3 [TDT3]DQ4 WE DROM
4-Mbit DRAM MSM514400C 1-Mbit DRAM MSM514256B
DI/O DROM RAS RAS
CAS VSS
RESET PDWN TEST DRAM/SR 4B/1B MSEL2 MSEL1 RSEL2 RSEL1 BR0 BR1 PDMD MCUM LOWPWR TEST
VDS
VD3
CAS0 CAS1 CAS2 CAS3 CAS4 CAS5 CAS6 CAS7
VD2
RECORDER IC CS1 CS2 CS3 CS4
VD1
HEX SW
VD0
MSM6789A
MIN
SW Phrase selection LIN
CA5 CA4 CA3 CA2 CA1 CA0 TST TCK TMD4
MOUT
ROM Speaker drive amplifier
APPLICATION CIRCUITS (for MSM6789A (5 V version)) (Continued)
XT
8.192 MHz
XT
LOUT AMON FIN FOUT ADIN AOUT
SGC SG
MON NAR SYNC TDT4-7 TMD0-3
+
+
This is an application circuit example when the MSM6789A is used in stand-alone mode with one 4-Mbit DRAM, four 1-Mbit DRAMs (4-bit type), and two 2-Mbit serial voice ROMs.
Semiconductor
DGND
AGND
Circuit 6 :
Application circuit in stand-alone mode with 4-Mbit DRAMs, 1-Mbit DRAM, and 2M-bit serial voice ROMs.
5 A0-A4 AVDD VCC A1(SADX) SADX SASX SADY A3(SAS) A0(SADY) A2(TAS) A4(RWCK) VCC VCC DVDD REC/PLAY DEL ST A0-A10 A0-A10 SP PAUSE WE RAS OE TEST
CAS VSS CAS VSS CS1 CS2 VSS
MSM6596A-XXX
Semiconductor
MSM5117400A
A0-A10 [TDT0]DQ1 [TDT1]DQ2 [TDT2]DQ3 [TDT3]DQ4 WE DROM DOUT RAS DI/O DROM CAS0 CAS1 CAS2 CAS3 CAS4 CAS5 CAS6 CAS7 2M Serial Voice ROM MSM6596A-XXX DQ1 DQ2 DQ3 DQ4 SASY TAS RDCK
16-Mbit DRAM MSM5117400A 11
11 A0-A10
RESET PDWN TEST DRAM/SR MSEL2 MSEL1 4B/1B RSEL2 RSEL1 BR0 BR1 PDMD LOWPWR MCUM TEST VDS VD3 VD2 VD1 VD0 MSM6789A MIN MOUT RECORDER IC
HEX SW
CS1 CS2 CS3 CS4
SW Phrase selection
CA5 CA4 CA3 CA2 CA1 CA0 TST TCK TMD4 LIN ROM XT XT
APPLICATION CIRCUITS (for MSM6789A (5 V version)) (Continued)
8.192 MHz
LOUT AMON FIN FOUT ADIN AOUT SGC SG
Speaker drive amplifier
MON NAR SYNC TDT4-7 TMD0-3 DGND AGND
+
+
MSM6789A/6789L
This is an application circuit example when the MSM6789A is used in stand-alone mode with two 16-Mbit DRAMs (4-bit type) and two 2-Mbit serial voice ROMs.
Circuit 7 :
Application circuit in stand-alone mode with 16-Mbit DRAMs and 2-Mbit serial voice ROMs.
DVDD REC/PLAY VCC
SADX
AVDD VCC SADX SASX SADY
DEL SAS SAS SAD SAS SADY TAS RWCK SASY TAS RDCK SADX
SADX
SAS
MSM6789A/6789L
MSM66V84B
MSM66V84B
MSM66V84B
ST SP PAUSE 4M Serial Register TAS RWCK WE DI/O DROM DOUT TEST
CS1 CS2 VSS
MSM6596A-XXX
SADY TAS
2M Serial Voice ROM MSM6596A-XXX
RESET PDWN TEST MSEL1 MSEL2
TAS
RWCK WE DI/O MSM66V84B RWCK WE DIN DOUT TEST RFSH NC RS/A CS VSS
RSEL1 RSEL2 BR0 BR1 PDMD MCUM TEST
DROM
VDS
CS1
DVDD
CS2
CS3
RECORDER IC
HEX SW
VD3 VD2 VD1 VD0
CS4
MIN
APPLICATION CIRCUITS (for MSM6789L (3.3 V Version))
MSM6789L
SW Phrase Selection
MOUT
CA5 CA4 CA3 CA2 CA1 CA0 TST TCK TMD4
LIN
ROM Speaker drive amplifier
XT
8.192 MHz
XT
LOUT AMON FIN FOUT ADIN AOUT
SGC
MON NAR SYNC TDT0-7 TMD0-3
SG
+
+
This is an application circuit example when the MSM6789L is used in stand-alone mode with four 4-Mbit serial registers and two 2-Mbit serial voice ROMs.
Semiconductor
DGND
AGND
Circuit 8 :
Application circuit in stand-alone mode with 4-Mbit serial registers and 2-Mbit serial voice ROMs.
Semiconductor
MSM6789A/6789L
MICROCONTROLLER INTERFACE MODE
FEATURES
* SBC method * Built-in 12-bit AD converter * Built-in 12-bit DA converter * Built-in microphone amplifier * Built-in low-pass filter Attenuation characteristics -40 dB/oct * External memories MSM6789A (5 V version) General-purpose DRAM, 32 Mbits maximum (for variable messages) 1-Mbit DRAM : Can be directly driven (MSM514256B, MSM511000B) 4-Mbit DRAM : Can be directly driven (MSM514400C, MSM514100C) 16-Mbit DRAM : Can be directly driven (MSM5117400A, MSM5116100A) ARAM, 32 Mbits maximum (for variable messages) Note: Use the first 64 Kbits with no failed bits for the ARAM. Serial register, 32 Mbits maximum (for variable messages) 4-Mbit serial register : Can be directly driven (MSM6684B) 8-Mbit serial register : Can be directly driven (MSM6685) MSM6789L (3.3 V version) Serial register, 16 Mbits maximum (for variable messages) 4-Mbit serial register: Can be directly driven (MSM66V84B) MSM6789A (5 V version) and MSM6789L (3.3 V version) Serial voice ROM, 4 Mbits maximum (for fixed messages) 1-Mbit serial voice ROM : Can be directly driven (MSM6595A) 2-Mbit serial voice ROM : Can be directly driven (MSM6596A) 3-Mbit serial voice ROM : Can be directly driven (MSM6597A) * Bit rate 10.0, 12.6, 16.0 kbps (at 8 kHz sampling freq.) 7.5, 9.5, 12.0 kbps (at 6 kHz sampling freq.) * Maximum recording time (when one 8-Mbit serial register is connected) 13.8 minutes (for 10.0 kbps SBC) 18.4 minutes (for 7.5 kbps SBC) 11.0 minutes (for 12.6 kbps SBC) 14.6 minutes (for 9.5 kbps SBC) 8.6 minutes (for 16.0 kbps SBC) 11.5 minutes (for 12.0 kbps SBC) * Number of phrases 63 phrases for variable messages 255 phrases for fixed messages * Standard linear PCM playback or OKI nonlinear PCM playback can be selected. * Voice triggered starting function (voice detect level can be set) * Uuvoiced-part elimination function (voice detect level can be set) * Pausing function * Master clock frequency: 6.0 MHz to 8.192 MHz * Power supply voltage: MSM6789A: Single 5 V power supply MSM6789L: Single 3.3 V power supply * Package options: MSM6789A: 100-pin plastic QFP (QFP100-P-1420-BK) (Product name: MSM6789AGS-BK) MSM6789L: 100-pin plastic QFP (QFP100-P-1420-BK) (Product name: MSM6789LGS-BK)
TST TCK
NAR VPM RPM BUSY
D3 D2 D1 D0
WR RD CE CE
TMD4 Status Register Microcontroller I/F Data I/O
TMD0 to TMD3
MSM6789A/6789L
TDT4 to TDT7
Test
DI/O DROM TDT0 to TDT3 [DQ1] to [DQ4]
SYNC
Circuit
TEST
TEST
Timing
Address Controller
Memory Controller
Controller SBC Analyzer/Synthesizer
BLOCK DIAGRAM (for MSM6789A (5 V Version))
MCUM RESET PDWN ACON EXTD MON DRAM/SR 4B/1B
A0(SADY) A1(SADX) A2(TAS) A3(SAS) A4(RWCK) A5 to A10 RAS CAS0 to CAS7 WE CS1 CS2 CS3 CS4
XT XT PCM Synthesizer
OSC
MIN
-
MSEL2 MSEL1 RSEL1 RSEL2 LOWPWR 12-bit DAC SG Circuit OSC (RC) DVDD AVDD DGND AGND
+ LPF 12-bit ADC
MOUT
LIN
- +
Semiconductor
LOUT
AMON FIN
AOUT FOUT
ADIN
SG SGC
Semiconductor
MSM6789A/6789L
PIN CONFIGURATION (TOP VIEW) (for MSM6789A (5 V Version))
CAS7 CAS6 CAS5 CAS4 CAS3 CAS2 CAS1 CAS0 XT XT DVDD RAS 4B/1B LOWPWR NC DROM CS4 CS3 CS2 CS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
[DQ4] [DQ3] [DQ2] [DQ1]
A10 A9 A8 A7 A6 A5 NC TMD4 TMD3 TMD2 TMD1 TMD0 TDT7 TDT6 TDT5 TDT4 TDT3 TDT2 TDT1 TDT0 SYNC TST TCK D0 D1 D2 D3 NC BUSY RPM
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A0 (SADY) A1 (SADX) A2 (TAS) A3 (SAS) A4 (RWCK) WE DI/O MON NAR TEST TEST TEST TEST DRAM/SR CE RD WR RESET TEST PDWN MSEL2 MSEL1 RSEL2 RSEL1 DGND AGND MIN MOUT LIN
VPM ACON TEST MCUM CE TEST EXTD TEST TEST DGND NC ADIN FOUT
100-Pin Plastic QFP ( ): [ ]: NC : Pins for connecting serial voice ROM. Pins for connecting 4-bit type DRAM. No-connection pin
AOUT FIN AMON AVDD SG SGC LOUT
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MSM6789A/6789L
Semiconductor
PIN DESCRIPTIONS (for MSM6789A (5 V Version))
Pin 90 47 40, 55 54 48, 49 53 51 52 50 46 45 43 42 44 Symbol DVDD AVDD DGND AGND SG, SGC MIN LIN MOUT LOUT AMON FIN FOUT ADIN AOUT Type -- -- -- -- O I O O I O I O pin and the DGND pin. Analog power supply. Insert a bypass capacitor of 0.1mF or more between this pin and the AGND pin. Digital ground. Analog ground. Output for analog circuit reference voltage (signal ground). Inverting input of the built-in OP amplifier. The non-inverting input pin is internally connected to SG (signal ground). Output of the built-in OP amplifier for MIN and LIN. Connected to the LOUT pin in the recording mode and to the DA converter output in the playback mode. This pin connects the built-in LPF input (FIN pin). Input of the built-in LPF. Output of the built-in LPF. This pin connects the AD converter input (ADIN pin). Input of the built-in 12-bit AD converter. Output of the built-in LPF. This pin outputs playback waveforms and connects an external speaker drive amplifier. This pin selects whether memory to be connected externally is DRAM or serial 66 DRAM/SR I register. Low level : Serial register High level : DRAM This pin selects either 1-bit type DRAM or 4-bit type DRAM. 88 4B/1B I Low level : 1-bit type High level : 4-bit type 79 78 A0 (SADY) A1 (SADX) These pins connect to A0 and A1 of DRAM at the time of DRAM selection. They also O connect to SAD pin of serial register and serial voice ROM at the time of serial register selection. These pins output leading addresses of read/write. This pin connects to A2 of DRAM at the time of DRAM selection. It also connects 77 A2 (TAS) O to TAS pin of serial register and serial voice ROM at the time of serial register selection. This pin is used to set serial addresses from the SADX and SADY pins into the internal address counter of the serial register and serial voice ROM. This pin connects to A3 of DRAM at the time of DRAM selection. It also connects 76 A3 (SAS) O to the SAS pin of the serial register and the SASX and SASY pins of the serial voice ROM at the time of serial register selection. Clock pin to write serial addresses. This pin connects to A4 of DRAM at the time of DRAM selection. It also connects 75 A4 (RWCK) O to the RWCK pin of the serial register and the RDCK pin of the serial voice ROM at the time of serial register selection. Clock pin to read data from and write data into the serial register. 1-6 A10-A5 O These pins connect to pins A5-A10 of DRAM at the time of DRAM selection. These pins output addresses of read/write. Description Digital power supply. Insert a bypass capacitor of 0.1mF or more between this
Semiconductor
MSM6789A/6789L
PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued)
Pin 74 73 85 89 93-100 81 82 83 84 58 59 Symbol Type WE DI/O DROM RAS CAS0CAS7 CS1 CS2 CS3 CS4 MSEL1 MSEL2 I I These pins select the capacity of the memory to be connected externally. These pins select the number of DRAMs and serial registers to be connected externallly. * When DRAM is selected (DRAM/SR = High level) MSEL2 L L L L L 56 57 RSEL1 RSEL2 I I L L L H H H H H H H H MSEL1 L L L L H H H H L L L L H H H H RSEL2 L L H H L L H H L L H H L L H H RSEL1 L H L H L H L H L H L H L H L H Memory capacity 1M 4 4M 1 1M 8 1M 4 + 4M 1 4M 2 4M 2 4M 3 4M 3 4M 4 16M 1 4M 6 4M 6 4M 8 4M 8 16M 2 16M 2 O Chip Slect. These pins connect CS pin of the serial register and the CS (CS1, CS2, CS3) pins of the serial voice ROM. O I/O I O O Description Write Enable. This pin connects to the WE pin of the serial register and DRAM. This pin selects either read or write mode. Data I/O. This pin connects to the DIN and DOUT pins of the serial register and DRAM. This pin is used to output write data and inputs read data. Data ROM. This pin connects to the DOUT pin of the serial voice ROM. This is a row address strobe pin of DRAM at the time of DRAM selection. These are the column address strobe pins of DRAM at the time of DRAM selection. CAS7, an addresss output pin, is connected to pin A11 of DRAM at the time of 16Mbit DRAM selection.
MSM6789A/6789L
Semiconductor
PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued)
Pin Symbol Type Description * When serial register is selected (DRAM/SR = Low level) MSEL2 L L 56 57 RSEL1 RSEL2 I I L L L L L L MSEL1 L L L L H H H H RSEL2 L L H H L L H H RSEL1 L H L H L H L H Memory capacity 4M 1 4M 2 4M 3 4M 4 8M 1 8M 2 8M 3 8M 4
This pin selects CAS-before-RAS refresh period of DRAM at the time of 87 LOWPWR I power down when DRAM is selected. Low level : 15 s max. High level : 125 s max. Mode Selection. 34 MCUM I Low level : Stand-alone mode High level : Microcontroller interface mode 62 RESET I A high input level causes the MSM6789A to be initialized and to go into the power down state. Power Down. When a low level is input the MSM6789A goes to the power down state. Unlike the RESET pin, this pin does not force the MSM6789A to be reset. 60 PDWN I When an Low level is applied to this pin during recording operation, the MSM6789A is halted, and will be maintained in the power down state while PDWN is low level. After this pin is restored to a high level, postprocessing for recording will be performed. 24 25 26 27 63 64 D0 D1 D2 D3 WR RD I I Write Pulse Input. Inputting a low pulse to WR pin causes a command or data to be input via D0 to D3 pins. Read Pulse Input. Inputting a low pulse to RD pin causes status bits or data to be output via D0 to D3 pins. Chip Enable Input. When the CE pin is set to low level and the CE pin is set to a 65 35 CE CE high level, the write pulse (WR) or read pulse (RD) can be accepted. I When the CE pin is set to a high level or CE pin is set to a low level, the write pulse (WR) and read pulse (RD) cannot be accepted so that data cannot be communicated via D0 to D3 pins. I/O Bidirectional data bus to transfer commands and data to and from an external microcontroller.
Semiconductor
MSM6789A/6789L
PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued)
Pin 29 Symbol BUSY Type O Description Busy. This pin outputs a high level while a command is being executed. When this pin is held high, do not apply any data to D0 to D3 pins. The state of this pin is the same as the contents of the BUSY bit of the status register. 30 RPM O RPM. This pin outputs a high level during recording or playback operation. The state of this pin is the same as the contents of the RPM bit of the status register. VPM. This pin outputs a high level during standby for voice incoming after the start of recording by voice triggered starting or unvoiced-part elimination. Also outputs a high 31 VPM O level when the record/playback is stopped temporarily by inputting the PAUSE command. The state of this pin is the same as the contents of the VPM bit of the status register. NAR. This NAR pin indicates whether the phrase designation by the CHAN command 71 NAR O is enabled or disabled. In the ROM play back operation, specify the next phrase after verifying that the NAR pin is at high level and input the START command. POP Noise Suppression Select. This pin selects whether the pop noise suppression circuit is used. 32 ACON I Low level : the pop noise suppression circuit is not used. High level : the pop noise suppression circuit is used. The DC level is shifted by the LEV command. 37 91 92 72 EXTD XT XT MON I I O O EXTD. In the record/playback operation by the EXT command, input a high level for read/write of SBC data. Input a low level for usual command input and status output. Oscillator Connect. When an external clock is used, input the clock through this pin. At the power-down state, this pin must be set to the ground level. Oscillator Connect. When an external clock is uesd, this pin must be left open. MON. This pin outputs a high level while the record/playback operation is being performed. Outputs a synchronizing clock while record/playback activated by the EXT command is being performed. 36, 37-39, TEST 61, 67-70 TEST 33 9-12 TMD3-TMD0 13-20 21 17-20 22 23 8
TDT7-TDT0 SYNC TDT3-TDT0 [DQ4]-[DQ1]
I
MSM6789A Test. Input a low level to the TEST pin and a high level to the TEST pin. MSM6789A Test. This pin must be left open. Connect these pins to DQ1 to DQ4 of DRAM at the time of 4-bit type DRAM selection. Otherwise these pins must be left open as they are MSM6789A test pins. MSM6789A Test. Input a low level.
I/O
I/O
TST TCK TMD4 I
MSM6789A/6789L
Semiconductor
ABSOLUTE MAXIMUM RATINGS (for MSM6789A (5 V Version))
Parameter Power supply voltage Input Voltage Storage temperature Symbol V DD V IN T STG Condition Ta=25C Ta=25C -- Rating -0.3 to +7.0 -0.3 ~ VDD +0.3 -55 to +150 Unit V V C
RECOMMENDED OPERATING CONDITIONS (for MSM6789A (5 V Version))
Parameter Power supply voltage Operating temperature Master clock frequencuy Symbol VDD Top fOSC Condition DGND=AGND=0 V -- -- Range +3.5 to +5.5*3 0 to +70 6.0 to 8.192 Unit V C MHz
ELECTRIAL CHARACTERISTICS (for MSM6789A (5 V Version))
DC Characteristics
Parameter High input voltage Low input voltage High output voltage Low output voltage High input current*1 High input current*2 Low input current*1 Low input current*2 Operating current consumption Symbol V IH V IL V OH V OL IIH1 IIH2 IIL1 IIL2 I DD IDDS1 Power down current IDDS2 IOH=-40 mA IOL=2 mA VIH=VDD VIH=VDD VIL=GND VIL=GND fOSC=8 MHz, no load No load Serial register connected No load DRAM connected Condition -- -- DVDD=AVDD=4.5 to 5.5 V*3 DGND=AGND=0 V Ta=0 to 70C Min. 0.8VDD -- V DD-0.3 -- -- -- -10 -20 -- -- -- Typ. -- -- -- -- -- -- -- -- 20 -- 200 Max. -- 0.2VDD -- 0.45 10 20 -- -- 35 10 -- V V mA mA mA mA mA mA mA Unit V V
*1 Applies to all inputs excluding the XT pin. *2 Applies to the XT pin. *3 The record/playback operation must be performed at the power supply voltage of 4.5 to 5.5 V. The MSM6789A operates at 3.5 to 5.5 V when the serial register is backed up.
Semiconductor Analog Characteristics
Parameter DA output relative error FIN admissible input voltage range FIN input impedance OP-amp open loop gain OP-amp input impedance OP-amp load resistance AOUT load resistance FOUT load resistance Symbol VDAE VFIN RFIN GOP RINA ROUTA RAOUT RFOUT Condition No load -- -- fIN=0 to 4 kHz -- -- -- --
MSM6789A/6789L
DVDD=AVDD=4.5 to 5.5 V DGND=AGND=0 V Ta=0 to 70C Min. -- 1 1 40 1 200 50 50 Typ. -- -- -- -- -- -- -- -- Max. 10 VDD-1 -- ---- -- -- -- Unit mV V MW dB MW kW kW kW
TST
TCK
NAR VPM RPM BUSY
D3 D2 D1 D0
WR RD CE CE
TMD4 Status Register Microcontroller I/F Data I/O TDT0 to TDT3
TMD0 to TMD3
DI/O DROM
MSM6789A/6789L
TDT4 to TDT7
Test
SYNC
Circuit
TEST
TEST
MCUM RESET Address Controller
PDWN
Timing
Memory Controller
ACON SBC Analyzer/Synthesizer
Controller
BLOCK DIAGRAM (for MSM6789L (3.3 V Version))
EXTD MON
SADY SADX TAS SAS RWCK WE CS1 CS2 CS3 CS4
XT XT PCM Synthesizer
OSC
MIN
-
MSEL2 MSEL1 RSEL1 RSEL2
+ LPF 12-bit ADC 12-bit DAC SG Circuit DVDD AVDD DGND AGND AOUT FOUT ADIN SG SGC
MOUT
LIN
- +
Semiconductor
LOUT
AMON FIN
Semiconductor
MSM6789A/6789L
PIN CONFIGURATION (TOP VIEW) (for MSM6789L (3.3V Version))
NC NC NC NC NC NC NC NC XT XT DVDD NC TEST TEST NC DROM CS4 CS3 CS2 CS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC NC NC NC NC NC NC TMD4 TMD3 TMD2 TMD1 TMD0 TDT7 TDT6 TDT5 TDT4 TDT3 TDT2 TDT1 TDT0 SYNC TST TCK D0 D1 D2 D3 NC BUSY RPM
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC SADY SADX TAS SAS RWCK WE DI/O MON NAR TEST TEST TEST TEST TEST CE RD WR RESET TEST PDWN MSEL2 MSEL1 RSEL2 RSEL1 DGND AGND MIN MOUT LIN
VPM ACON TEST MCUM CE TEST EXTD TEST TEST DGND NC ADIN FOUT
100-Pin Plastic QFP NC : No-connection pin
AOUT FIN AMON AVDD SG SGC LOUT
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MSM6789A/6789L
Semiconductor
PIN DESCRIPTIONS (for MSM6789L (3.3 V Version))
Pin 90 47 40, 55 54 48, 49 53 51 52 50 46 45 43 42 44 79 78 77 Symbol DVDD AVDD DGND AGND SG, SGC MIN LIN MOUT LOUT AMON FIN FOUT ADIN AOUT SADY SADX TAS Type -- -- -- -- O I O O I O I O O pin and the DGND pin. Analog power supply. Insert a bypass capacitor of 0.1mF or more between this pin and the AGND pin. Digital ground. Analog ground. Output for analog circuit reference voltage (signal ground). Inverting input of the built-in OP amplifier. The non-inverting input pin is internally connected to SG (signal ground). Output of the built-in OP amplifier for MIN and LIN. Connected to the LOUT pin in the recording mode and to the DA converter output in the playback mode. This pin connects the built-in LPF input (FIN pin). Input of the built-in LPF. Output of the built-in LPF. This pin connects the AD converter input (ADIN pin). Input of the built-in 12-bit AD converter. Output of the built-in LPF. This pin outputs playback waveforms and connects an external speaker drive amplifier. These pins connect to SAD pin of serial register and serial voice ROM. These pins output leading addresses of read/write. This pin connects to TAS pin of serial register and serial voice ROM. This pin is used O to set serial addresses from the SADX and SADY pins into the internal address counter of the serial register and serial voice ROM. 76 75 74 73 85 81 82 83 84 58 59 SAS RWCK WE DI/O DROM CS1 CS2 CS3 CS4 MSEL1 MSEL2 I I These pins select the capacity of the memory to be connected externally. O Chip Slect. These pins connect CS pin of the serial register and the CS (CS1, CS2, CS3) pins of the serial voice ROM. O O O I/O I This pin connects to the SAS pin of the serial register and the SASX and SASY pins of the serial voice ROM. Clock pin to write serial addresses. This pin connects to the RWCK pin of the serial register and the RDCK pin of the serial voice ROM. Clock pin to read data from and write data into the serial register. Write Enable. This pin connects to the WE pin of the serial register and DRAM. This pin selects either read or write mode. Data I/O. This pin connects to the DIN and DOUT pins of the serial register and DRAM. This pin is used to output write data and inputs read data. Data ROM. This pin connects to the DOUT pin of the serial voice ROM. Description Digital power supply. Insert a bypass capacitor of 0.1mF or more between this
Semiconductor
MSM6789A/6789L
PIN DESCRIPTIONS (for MSM6789L (3.3 V Version)) (Continued)
Pin Symbol Type externallly. 56 57 RSEL1 RSEL2 I I MSEL2 L L L L Mode Selection. 34 MCUM I Low level : Stand-alone mode High level : Microcontroller interface mode 62 RESET I A high input level causes the MSM6789L to be initialized and to go into the power down state. Power Down. When a low level is input the MSM6789L goes to the power down state. Unlike the RESET pin, this pin does not force the MSM6789L to be reset. 60 PDWN I When an Low level is applied to this pin during recording operation, the MSM6789L is halted, and will be maintained in the power down state while PDWN is low level. After this pin is restored to a high level, postprocessing for recording will be performed. 24 25 26 27 63 64 D0 D1 D2 D3 WR RD I I Write Pulse Input. Inputting a low pulse to WR pin causes a command or data to be input via D0 to D3 pins. Read Pulse Input. Inputting a low pulse to RD pin causes status bits or data to be output via D0 to D3 pins. Chip Enable Input. When the CE pin is set to low level and the CE pin is set to a 65 35 CE CE high level, the write pulse (WR) or read pulse (RD) can be accepted. I When the CE pin is set to a high level or CE pin is set to a low level, the write pulse (WR) and read pulse (RD) cannot be accepted so that data cannot be communicated via D0 to D3 pins. Busy. This pin outputs a high level while a command is being executed. When this 29 BUSY O pin is held high, do not apply any data to D0 to D3 pins. The state of this pin is the same as the contents of the BUSY bit of the status register. 30 RPM O RPM. This pin outputs a high level during recording or playback operation. The state of this pin is the same as the contents of the RPM bit of the status register. I/O Bidirectional data bus to transfer commands and data to and from an external microcontroller. MSEL1 L L L L RSEL2 L L H H RSEL1 L H L H Memory capacity 4M 4M 4M 4M 1 2 3 4 Description These pins select the number of serial registers to be connected
MSM6789A/6789L
Semiconductor
PIN DESCRIPTIONS (for MSM6789L (3.3 V Version)) (Continued)
Pin Symbol Type Description VPM. This pin outputs a high level during standby for voice incoming after the start of recording by voice triggered starting or unvoiced-part elimination. Also outputs a high 31 VPM O level when the record/playback is stopped temporarily by inputting the PAUSE command. The state of this pin is the same as the contents of the VPM bit of the status register. NAR. This NAR pin indicates whether the phrase designation by the CHAN command 71 NAR O is enabled or disabled. In the ROM play back operation, specify the next phrase after verifying that the NAR pin is at high level and input the START command. POP Noise Suppression Select. This pin selects whether the pop noise suppression circuit is used. 32 ACON I Low level : the pop noise suppression circuit is not used. High level : the pop noise suppression circuit is used. The DC level is shifted by the LEV command. 37 91 92 72 EXTD XT XT MON I I O O EXTD. In the record/playback operation by the EXT command, input a high level for read/write of SBC data. Input a low level for usual command input and status output. Oscillator Connect. When an external clock is used, input the clock through this pin. At the power-down state, this pin must be set to the ground level. Oscillator Connect. When an external clock is uesd, this pin must be left open. MON. This pin outputs a high level while the record/playback operation is being performed. Outputs a synchronizing clock while record/playback activated by the EXT command is being performed. 36, 37-39, TEST 61, 67-70 TEST 33 9-12 TMD3-TMD0 13-20 21 17-20 22 23 8
TDT7-TDT0 SYNC TDT3-TDT0
I
MSM6789L Test. Input a low level to the TEST pin and a high level to the TEST pin. MSM6789L Test. This pin must be left open. These pins must be left open as they are MSM6789L test pins. MSM6789L Test. Input a low level.
I/O I/O I
TST TCK TMD4
Semiconductor
MSM6789A/6789L
ABSOLUTE MAXIMUM RATINGS (for MSM6789L (3.3 V Version))
Parameter Power supply voltage Input Voltage Storage temperature Symbol VDD VIN TSTG Condition Ta=25C Ta=25C -- Rating -0.3 to +7.0 -0.3 ~ VDD +0.3 -55 to +150 Unit V V C
RECOMMENDED OPERATING CONDITIONS (for MSM6789L (3.3 V Version))
Parameter Power supply voltage Operating temperature Master clock frequencuy Symbol VDD Top fOSC Condition DGND=AGND=0 V -- -- Range +3.0 to +3.6 0 to +70 6.0 to 8.192 Unit V C MHz
ELECTRIAL CHARACTERISTICS (for MSM6789L (3.3 V Version))
DC Characteristics
Parameter High input voltage Low input voltage High output voltage Low output voltage High input current*1 High input current*2 Low input current*1 Low input current*2 Operating current consumption Symbol VIH VIL VOH VOL IIH1 IIH2 IIL1 IIL2 IDD IDDS1 Power down current IDDS2 IOH=-40 mA IOL=2 mA VIH=VDD VIH=VDD VIL=GND VIL=GND fOSC=8 MHz, no load No load Serial register connected No load DRAM connected Condition -- -- DVDD=AVDD=3.0 to 3.6 V DGND=AGND=0 V Ta=0 to 70C Min. 0.85VDD -- VDD-0.3 -- -- -- -10 -20 -- -- -- Typ. -- -- -- -- -- -- -- -- 20 -- 200 Max. -- 0.15VDD -- 0.45 10 20 -- -- 35 10 -- Unit V V V V mA mA mA mA mA mA mA
*1 Applies to all inputs excluding the XT pin. *2 Applies to the XT pin.
MSM6789A/6789L
Semiconductor
Analog Characteristics
Parameter DA output relative error FIN admissible input voltage range FIN input impedance OP-amp open loop gain OP-amp input impedance OP-amp load resistance AOUT load resistance FOUT load resistance Symbol VDAE VFIN RFIN GOP RINA ROUTA RAOUT RFOUT Condition No load -- -- fIN=0 to 4 kHz -- -- -- --
DVDD=AVDD=3.0 to 3.6 V DGND=AGND=0 V Ta=0 to 70C Min. -- 1 1 40 1 400 100 100 Typ. -- -- -- -- -- -- -- -- Max. 20 VDD-1 -- ---- -- -- -- Unit mV V MW dB MW kW kW kW
DVDD VCC
SADX
AVDD SADX SADX SASX SADY SAS SADY TAS RWCK VCC
D3 D2 D1 D0 MSM6685 MSM6685 MSM6685 SAS SAS SAD
SADX
SAS TAS TAS RWCK WE DI/O DROM DOUT TEST
CS1 CS2 VSS
Semiconductor
MSM6596A-XXX
APPLICATION CIRCUITS (for MSM6789A (5 V Version))
8.192 MHz
This is an application circuit example when the MSM6789A is used in microcontroller interface mode with four 8-Mbit serial registers and two 2-Mbit serial voice ROMs.
Microcontroller 2M Serial Voice ROM MSM6596A-XXX SASY TAS RDCK RWCK WE DIN DOUT TEST RFSH NC RS/A CS VSS 8M Serial Register MSM6685
RD WR CE
SADY
RESET PDWN
TAS
RWCK WE DI/O DROM
MCUM LOWPWR DRAM/SR A5-A10 MSEL2 RAS MSEL1 CAS0-CAS7 RSEL1 RSEL2 CE CS1 TEST 4B/1B CS2 ACON CS3 EXTD TST CS4 TCK TEST MIN BUSY RPM VPM MOUT SYNC TDT0-7 TMD0-3 TMD4 LIN XT
RECORDER IC
MSM6789A
XT
MON NAR
LOUT AMON FIN FOUT ADIN AOUT
Speaker drive amplifier
SGC
MSM6789A/6789L
DGND
AGND
SG
+
+
Circuit 1 :
Application circuit in microcontroller interface mode with 8-Mbit serial registers and 2-Mbit serial voice ROMs.
DVDD SADX
AVDD
VCC VCC
VCC
VCC
VCC SADX SASX SADY
MSM6596A-XXX
MSM514100A
SAS SADY TAS RWCK SASY TAS RDCK
MSM514100A
MSM514100A
4-Mbit DRAM
MSM6789A/6789L
D3 D2 D1 D0
2M Serial Voice ROM MSM6596A-XXX
APPLICATION CIRCUITS (for MSM6789A (5 V Version)) (Continued)
8.192 MHz Speaker drive amplifier
This is an application circuit example when the MSM6789A is used in microcontroller interface mode with four 4-Mbit DRAMs (1-bit type) and two 2-Mbit serial voice ROMs.
Microcontroller MSM514100A
DROM DOUT TEST
CAS VSS CAS VSS CAS VSS CS1 CS2 VSS CAS VSS
RD WR CE
RESET PDWN
A0(SADY) A1(SADX) A2(TAS) A3(SAS) A4(RWCK) A5 A6 A7 A8 A9 A10 WE DI/O DROM RAS
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 WE DI/O A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 WE DIN DOUT RAS
CAS0 CAS1 CAS2 CAS3 CAS4 CAS5 CAS6 CAS7
CS1 CS2 CS3 CS4
MCUM TEST CE DRAM/SR MSEL2 MSEL1 RSEL2 RSEL1 LOWPWR 4B/1B ACON EXTD TST TCK TEST
RECORDER IC MSM6789A
MIN
BUSY RPM VPM SYNC TMD4
MOUT
LIN
XT
XT
LOUT AMON FIN FOUT ADIN AOUT
MON NAR TDT0-7 TMD0-3
SGC
Semiconductor
DGND
AGND
SG
+
+
Circuit 2 :
Application circuit in microcontroller interface mode with 4-Mbit DRAMs and 2-Mbit serial voice ROMs.
5 A0-A4
DVDD A1(SADX) SADX SASX SADY A3(SAS) A0(SADY) A2(TAS) MSM511000A MSM511000A MSM511000A
AVDD
VCC VCC VCC VCC VCC VCC
MSM6596A-XXX
11 10 A0-A9 10 10 10
Semiconductor
D3 D2 D1 D0 SASY TAS A4(RWCK) RDCK 2M Serial Voice ROM MSM6596A-XXX
A0-A10
A0-A10
4-Mbit DRAM MSM514100A
1-Mbit DRAM MSM511000A
APPLICATION CIRCUITS (for MSM6789A (5 V Version)) (Continued)
8.192 MHz Speaker drive amplifier
This is an application circuit example when the MSM6789A is used in microcontroller interface mode with one 4-Mbit DRAM, four 1-Mbit DRAMs (1-bit type), and two 2-Mbit serial voice ROMs.
Microcontroller DROM DOUT TEST
CAS VSS CAS VSS CAS VSS CAS VSS CS1 CS2 VSS
RD WR CE WE DIN DOUT RAS CAS VSS
RESET PDWN
WE DI/O DROM RAS
CAS0 CAS1 CAS2 CAS3 CAS4 CAS5 CAS6 CAS7
RECORDER IC
MCUM TEST CE LOWPWR DRAM/SR MSEL2 MSEL1 RSEL2 RSEL1 ACON EXTD TST TCK TEST 4B/1B
CS1 CS2 CS3 CS4
MSM6789A
MIN
BUSY RPM VPM SYNC TMD4
MOUT
LIN
XT
XT
LOUT AMON FIN FOUT ADIN
AOUT
MON NAR TDT0-7 TMD0-3
SGC
MSM6789A/6789L
DGND
AGND
SG
+
+
Circuit 3 :
Application circuit in microcontroller interface mode with 4-Mbit DRAMs, 1-Mbit DRAMs, and 2-Mbit serial voice ROMs.
5 A0-A4 DVDD AVDD A1(SADX) SADX SASX SADY A3(SAS) A0(SADY) A2(TAS) A4(RWCK) VCC VCC VCC
MSM6596A-XXX
MSM5116100A
11 A0-A10 A0-A10 A11 A0-A10 A0-A10
MSM6789A/6789L
16-Mbit DRAM 11 SASY TAS RDCK 2M Serial Voice ROM MSM6596A-XXX
D3 D2 D1 D0 RD WR CE DROM DOUT TEST
CAS VSS CS1 CS2 VSS
APPLICATION CIRCUITS (for MSM6789A (5 V Version)) (Continued)
8.192 MHz
This is an application circuit example when the MSM6789A is used in microcontroller interface mode with two 16-Mbit DRAMs (1-bit type) and two 2-Mbit serial voice ROMs.
Microcontroller MSM5116100A RESET PDWN CAS0 CAS1 CAS2 CAS3 CAS4 CAS5 CAS6 CAS7 CS1 CS2 CS3 CS4 MIN MOUT
CAS VSS
WE DI/O DROM RAS
WE DIN DOUT RAS
RECORDER IC MSM6789A LIN
MCUM TEST CE LOWPWR DRAM/SR MSEL2 MSEL1 RSEL2 RSEL1 4B/1B ACON EXTD TST TCK TEST BUSY RPM VPM SYNC TMD4
XT XT
LOUT AMON FIN FOUT ADIN
Speaker drive amplifier
Semiconductor
MON AOUT NAR TDT0-7 SGC TMD0-3 SG DGND AGND
+
+
Circuit 4 :
Application circuit in microcontroller interface mode with 16-Mbit DRAMs and 2-Mbit serial voice ROMs.
5
DVDD A1(SADX) SADX SASX SADY MSM6596A-XXX A3(SAS) A0(SADY) A2(TAS) A4(RWCK) SASY TAS RDCK 2M Serial Voice ROM MSM6596A-XXX MSM514400C MSM514400C MSM514400C 10 10 10
AVDD
VCC VCC
VCC
VCC
VCC
Semiconductor
D3 D2 D1 D0 DQ1 DQ2 DQ3 DQ4 DROM DOUT TEST
CAS VSS CAS VSS CAS VSS CS1 CS2 VSS
A0-A9 A10
10
4-Mbit DRAM MSM514400C
APPLICATION CIRCUITS (for MSM6789A (5 V Version)) (Continued)
8.192 MHz Speaker drive amplifier
This is an application circuit example when the MSM6789A is used in microcontroller interface mode with four 4-Mbit DRAMs (4-bit type) and two 2-Mbit serial voice ROMs.
Microcontroller WE RAS OE
CAS VSS
RD WR CE
[TDT0]DQ1 [TDT1]DQ2 [TDT2]DQ3 [TDT3]DQ4
RESET PDWN
WE RAS DI/O DROM
CAS0 CAS1 CAS2 CAS3 CAS4 CAS5 CAS6 CAS7
RECORDER IC
MCUM TEST CE DRAM/SR 4B/1B MSEL2 MSEL1 RSEL2 RSEL1 LOWPWR ACON EXTD TST TCK TEST
CS1 CS2 CS3 CS4
MSM6789A
MIN
BUSY RPM VPM SYNC TMD4
MOUT
LIN
XT
XT
LOUT AMON FIN FOUT ADIN AOUT
MON NAR TDT4-7 TMD0-3
SGC
MSM6789A/6789L
DGND
AGND
SG
+
+
Circuit 5 :
Application circuit in microcontroller interface mode with 4-Mbit DRAMs and 2-Mbit serial voice ROMs.
5 A0-A4
DVDD A1(SADX) SADX SASX SADY A3(SAS) A0(SADY) A2(TAS) MSM514256B MSM514256B MSM514256B
AVDD
VCC VCC VCC VCC VCC VCC
MSM6596A-XXX
MSM6789A/6789L
D3 D2 D1 D0 9 A0-A8 9 9 9 SASY TAS A4(RWCK) RDCK 2M Serial Voice ROM MSM6596A-XXX
A0-A9
10
A0-A9
4-Mbit DRAM MSM514400C
1-Mbit DRAM MSM514256B
APPLICATION CIRCUITS (for MSM6789A (5 V Version)) (Continued)
8.192 MHz Speaker drive amplifier
This is an application circuit example when the MSM6789A is used in microcontroller interface mode with one 4-Mbit DRAM, four 1-Mbit DRAMs (4-bit type), and two 2-Mbit serial voice ROMs.
Microctontroller DQ1 DQ2 DQ3 DQ4 WE OE DROM DOUT TEST
CAS VSS CAS VSS CAS VSS CAS VSS CS1 CS2 VSS
RD WR CE
RESET PDWN RAS
CAS VSS
A10 [TDT0]DQ1 [TDT1]DQ2 [TDT2]DQ3 [TDT3]DQ4 WE DI/O DROM RAS
CAS0 CAS1 CAS2 CAS3 CAS4 CAS5 CAS6 CAS7
CS1 CS2 CS3 CS4
RECORCDER IC
MCUM TEST CE 4B/1B DRAM/SR LOWPWR RSEL2 RSEL1 MSEL2 MSEL1 ACON EXTD TST TCK TEST
MIN
MSM6789A
BUSY RPM VPM SYNC TMD4
MOUT
LIN
XT
XT
LOUT AMON FIN FOUT ADIN
AOUT
MON NAR TDT4-7 TMD0-3
SGC
Semiconductor
DGND
AGND
SG
+
+
Circuit 6 :
Application circuit in microcontroller interface mode with 4-Mbit DRAM, 1-Mbit DRAMs, and 2-Mbit serial voice ROMs.
5 A0-A4 DVDD AVDD A1(SADX) SADX SASX SADY A3(SAS) A0(SADY) A2(TAS) A4(RWCK) VCC VCC VCC
MSM6596A-XXX
MSM5117400A
11 A0-A10 A0-A10 A0-A10 A0~A10
16-Mbit DRAM 11 SASY TAS RDCK 2M Serial Voice ROM MSM6596A-XXX
Semiconductor
D3 D2 D1 D0 RD WR CE DROM DOUT TEST
CAS VSS CS1 CS2 VSS
APPLICATION CIRCUITS (for MSM6789A (5 V Version)) (Continued)
8.192 MHz
This is an application circuit example when the MSM6789A is used in microcontroller interface mode with two 16-Mbit DRAMs (4-bit type) and two 2-Mbit serial voice ROMs.
Microcontroller RESET PDWN RAS
CAS VSS
[TDT0]DQ1 [TDT1]DQ2 [TDT2]DQ3 [TDT3]DQ4 WE DI/O DROM RAS DQ1 DQ2 DQ3 DQ4 WE OE MSM5117400A CAS0 CAS1 CAS2 CAS3 CAS4 CAS5 CAS6 CAS7 RECORDER IC CS1 CS2 CS3 CS4 MIN MOUT MSM6789A LIN
MCUM TEST CE LOWPWR 4B/1B DRAM/SR MSEL2 MSEL1 RSEL2 RSEL1 ACON EXTD TST TCK TEST BUSY RPM VPM SYNC TMD4
XT XT
LOUT AMON FIN FOUT ADIN
Speaker drive amplifier
MSM6789A/6789L
MON AOUT NAR TDT4-7 SGC TMD0-3 SG DGND AGND
+
+
Circuit 7 :
Application circuit in microcontroller interface mode with 16-Mbit DRAMs and 2-Mbit serial voice ROMs.
DVDD
AVDD
D3 D2 D1 D0 A1(SADX) A3(SAS) A0(SADY) A2(TAS) A4(RWCK) WE DI/O RD WR CE RESET EXTD
MSM6789A/6789L
APPLICATION CIRCUITS (for MSM6789A (5 V Version)) (Continued)
8.192 MHz
This is an application circuit example when the EXT command is used for recording/playback.
Microcontroller PDWN MCUM LOWPWR DROM DRAM/SR RAS MSEL1 MSEL2 CAS0-CAS7 RSEL1 A5-A10 RSEL2 CE CS1 TEST CS2 ACON 4B/1B CS3 TST TCK CS4 TEST RECORDER IC MSM6789A MIN MOUT BUSY RPM VPM SYNC TDT0-7 TMD0-3 TMD4 LIN XT XT MON NAR SGC DGND AGND SG LOUT AMON FIN FOUT ADIN AOUT Speaker drive amplifier
+
+
Semiconductor
Circuit 8 :
Application circuit when EXT command is used.
DVDD VCC
SADX
AVDD SADX SADX SASX SADY SAS SADY TAS RWCK VCC
D3 D2 D1 D0 SAS SAS SAD MSM66V84B MSM66V84B MSM66V84B
SADX
SAS TAS TAS RWCK WE DI/O DROM DOUT TEST
CS1 CS2 VSS
Semiconductor
MSM6596A-XXX
APPLICATION CIRCUITS (for MSM6789L (3.3 V Version))
8.192 MHz
This is an application circuit example when the MSM6789L is used in microcontroller interface mode with four 4-Mbit serial registers and two 2-Mbit serial voice ROMs.
Microcontroller 2M Serial Voice ROM MSM6596A-XXX SASY TAS RDCK RWCK WE DIN DOUT TEST RFSH NC RS/A CS VSS 4M Serial Register MSM66V84B
RD WR CE
SADY
RESET PDWN
TAS
RWCK WE DI/O DROM
MCUM LOWPWR DRAM/SR A5-A10 MSEL2 RAS MSEL1 CAS0-CAS7 RSEL1 RSEL2 CE CS1 TEST 4B/1B CS2 ACON CS3 EXTD TST CS4 TCK TEST MIN BUSY RPM VPM MOUT SYNC TDT0-7 TMD0-3 TMD4 LIN XT
RECORDER IC
MSM6789L
XT
MON NAR
LOUT AMON FIN FOUT ADIN AOUT
Speaker drive amplifier
SGC
MSM6789A/6789L
DGND
AGND
SG
+
+
Circuit 9 :
Application circuit in microcontroller interface mode with 4-Mbit serial registers and 2-Mbit serial voice ROMs.

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